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MX23L6422
3.3 Volt 64M-BIT (4M x 16 / 2M x 32) Mask ROM with Page Mode
FEATURES
* Bit organization - 4M x 16 (byte mode) - 2M x 32 (double word mode) * Fast access time - Random access: 110ns (max.) for 3.135~3.6V 120ns (max.) for 3.0~3.6V - Page access: 30ns (max.) * Page Size - 8 double words per page * Current - Operating: 60mA (max.) - Standby: 20uA (max.) * Supply voltage - 3.3V10% * Package - 70 pin SSOP
ORDER INFORMATION
Part No. MX23L6422MC-11 MX23L6422MC-12 Access Page Access Package Time 110ns 120ns Time 30ns 50ns 30ns 50ns 70 pin SSOP 70 pin SSOP 70 pin SSOP (pb free) MX23L6422MC-12G 120ns 70 pin SSOP (pb free)
MX23L6422MC-11G 110ns
PIN CONFIGURATION
70 SSOP
A0 A1 A2 A3 A4 A5 VCC D0 D16 D1 D17 VSS VCC D2 D18 D3 D19 D4 D20 D5 D21 VSS VCC D6 D22 D7 D23 VSS A6 A7 A8 A9 A10 A11 A12 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 NC NC A20 WORD OE CE VSS D31/A-1 D15 D30 D14 VSS VCC D29 D13 D28 D12 D27 D11 D26 D10 VSS VCC D25 D9 D24 D8 VCC A19 A18 A17 A16 A15 A14 A13
PIN DESCRIPTION
Symbol A0~A20 D0~D30 D31/A-1 CE OE WORD VCC VSS NC Pin Function Address Inputs Data Outputs D31 (Double Word Mode)/ LSB Address (Word Mode) Chip Enable Input Output Enable Input Double Word/ Word Mode Selection Power Supply Pin Ground Pin No Connection
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MODE SELECTION CE H L L L OE X H L L WORD X X H L D31/A-1 X X Output Input D0~D15 High Z High Z D0~D15 D0~D15 D16~D31 High Z High Z D16~D31 High Z Mode Double Word Word Power Stand-by Active Active Active
BLOCK DIAGRAM
A0/(A-1) A2 A3 A20 CE WORD OE Address Buffer Memory Array Page Buffer Page Decoder Double Word/ Word Output Buffer D0 D31/(D15)
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ABSOLUTE MAXIMUM RATINGS
Item Voltage on any Pin Relative to VSS Ambient Operating Temperature Storage Temperature Symbol VIN Topr Tstg Ratings -1.3V to 4.1V 0 C to 70 C -65 C to 125 C
Note: Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to 1.3V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC+0.5V. During voltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns.
DC CHARACTERISTICS (Ta = 0 C ~ 70 C, VCC = 3.3V10%)
Item Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Operating Current Symbol VOH VOL VIH VIL ILI ILO ICC1 MIN. 2.4V 2.2V -0.3V MAX. 0.4V VCC+0.3V 0.8V 10uA 10uA 60mA Conditions IOH = -0.4mA IOL = 1.6mA
Standby Current (TTL) Standby Current (CMOS) Input Capacitance Output Capacitance
ISTB1 ISTB2 CIN COUT
-
1mA 20uA 10pF 10pF
0V, VCC 0V, VCC tRC = 110ns, all output open, with normal sequential access testing pattern CE = VIH CE>VCC-0.2V Ta = 25 C, f = 1MHZ Ta = 25 C, f = 1MHZ
AC CHARACTERISTICS (Ta = 0 C ~ 70 C, VCC = 3.3V10%)
Item Read Cycle Time Address Access Time Chip Enable Access Time Page Mode Access Time Output Enable Time Output Hold After Address Output High Z Delay Symbol tRC tAA tACE tPA tOE tOH tHZ 23L6422-11* MIN. MAX. 110ns 100ns 110ns 30ns 30ns 0ns 20ns 23L6422-12 MIN. MAX. 120ns 120ns 120ns 50ns 50ns 0ns 20ns
Note: Output high-impedance delay (tHZ) is measured from OE or CE going high, and this parameter guaranteed by design over the full voltage and temperature operating range - not tested. * 110ns for 3.135~3.6V
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AC Test Conditions
Input Pulse Levels Input Rise and Fall Times Input Timing Level Output Timing Level Output Load 0.4V~ 2.4V 10ns 1.4V 1.4V See Figure
IOH (load)=-0.4mA DOUT IOL (load)=1.6mA
C<100pF
Note:No output loading is present in tester load board. Active loading is used and under software programming control.
TIMING DIAGRAM
RANDOM READ
ADD
Output loading capacitance includes load board's and all stray capacitance.
ADD
tACE
ADD
tRC
ADD
CE
tOE
OE
tAA tOH tHZ
DATA
VALID
VALID
VALID
PAGE READ
A3-A20
VALID ADD
(A-1),A0,A1,A2
1'st ADD tAA
2'nd ADD tPA VALID VALID
3'rd ADD
DATA
VALID
Note: CE, OE are enable. Page size is 8 double words in 32-bit mode, 16 words in 16-bit mode.
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PACKAGE INFORMATION
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REVISION HISTORY
REVISION 2.1 2.2 DESCRIPTION AC CHARACTERISTICS tOH 10ns-->0ns Add new 86pin TSOP(2) package Add 100ns speed grade Delete 115ns speed grade Change 100ns speed grade to 110ns Add 110ns(max.) for 3.15~3.6V ; 120ns(max.) for 3.0~3.6V Modify Operating Current : 40mA-->60mA Modify Pin Configuration--100 TQFP D31-->D31/A-1; 86 TSOP NC-->D31/A-1 Delete package:100 pin TQFP Add Package Information Modify 110ns for 3.15~3.6V --> 3.135~3.6V Deleted 86-pin TSOP Added Pb-free in order information PAGE P4 P1 P1,2 P4 P4 P1 P1,3 P2 P1,2 P5,6 P1,3 P1 P1 DATE JAN/29/1999 APR/09/1999
2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1
SEP/14/1999 DEC/29/1999 JAN/13/2000 DEC/26/2000 OCT/19/2001 MAY/31/2002 AUG/07/2002 OCT/31/2002 JUN/02/2003
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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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